Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture
نویسندگان
چکیده
This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP).
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تاریخ انتشار 2006